1. Field of the Invention
The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly, to a chip package structure and fabricating method thereof.
2. Description of Related Art
In the semiconductor industry, the fabrication of an integrated circuit (IC) is mainly divided into three stages: IC design, IC process and IC package.
During the fabrication of ICs, a chip is made by the steps of wafer fabricating, IC forming, wafer sawing and so on. The wafer has an active surface, which generally refers to a surface having active devices formed thereon. When the IC on the wafer is finished, a plurality of bonding pads is further disposed on the active surface of the wafer, such that the chip formed by wafer sawing is electrically connected to a carrier outward via the bonding pads. The carrier is, for example, a lead frame or a package substrate. The chip can be electrically connected to the carrier by means of wire bonding or flip-chip bonding, such that the bonding pads of the chip are electrically connected to the contacts of the carrier, thus forming a chip package structure.
FIG. 1A is a schematic sectional side view of a conventional chip package structure. FIG. 1B is a schematic top view of a portion of the members of the chip package structure in FIG. 1A. Referring to FIGS. 1A and 1B, a conventional chip package structure 100 includes a chip 110, a lead frame 120, a plurality of first bonding wires 130, a plurality of second bonding wires 140, a plurality of third bonding wires 150 and an encapsulant 160. The chip 110 has an active surface 112 and a plurality of first bonding pads 114 and second bonding pads 116 disposed on the active surface 112. The chip 110 is fixed below the lead frame 120, and the lead frame 120 includes a plurality of inner leads 122 and a bus bar 124. The inner leads 122 and the bus bar 124 are located above the active surface 112 of the chip 110, and the bus bar 124 is in an annular shape.
Referring to FIG. 1B, as the first bonding pads 114 of the chip 110 have the same electric potential, and the first bonding pads 114 are, for example, ground bonding pads or power supply bonding pads, thus the first bonding pads 114 having the same electric potential are respectively connected to the bus bar 124 via the first bonding wires 130, and the bus bar 124 is further connected to the corresponding portion of the inner leads 122 via the second bonding wires 140. However, the second bonding pads 116 of the chip 110 for transmitting signals (for example, signal bonding pads with ever-changing electric potentials) must be connected to other corresponding inner leads 122 via the third bonding wires 150, and the third bonding wires 150 usually have to cross a portion of the first bonding wires 130, a portion of the second bonding wires 140 and the bus bar 124. Therefore, the third bonding wires 150 are quite long, which is likely to make the third bonding wires 150 collapsed, thereby causing electric shorts. Or, the third bonding wires 150 may be collapsed during molding or being pulled apart by the injected encapsulant, thus causing electric broken circuits.